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Tech: Low Voltage Digital Logic Circuits


The current waves in the developments of electronic devices, especially in their movement towards mobility, focus on the requirement for energy efficiency abreast with productivity. The low consumption of the circuits used in mobile devices represents a large industry. The implementation of low-energy circuits can be seen at the stage of digital logic design. Analyzing such topics the present paper will provide a summary of low voltage, digital logical designs, based on a review of three scholarly articles.

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In the article, “Ultralow-Voltage, Minimum-Energy CMOS” by Hanson et al (2006), the authors explain energy efficiency requirements in circuit design by focusing on supply-voltage scaling. The authors argue that due to gate leakage and the rise of sub-threshold new strategies are required. The authors’ strategy of low-consumption is provided based on exploring a minimum-energy CMOS, according to which low-energy operations can be achieved through several architectural techniques.

The general approach toward minimizing consumption can be seen through the presented model of energy-optimal supply voltage, Vmin –“ the tradeoff between leakage energy and dynamic energy that occurs in energy-optimal circuits”, where energy efficiency is reached through reducing Vmin until it reaches the minimum functional voltage (Hanson et al. 470). One technique can be seen through placing specific voltage islands that enable targeting energy optimal conditions on a block by block basis, where different blocks will have different Vmin values.

Another technique is using adaptive body biasing (ABB), i.e. modulating the voltage of the substrate, where Vmin can be lowered through reducing stand-by mode leakage, and accordingly raising transistor utility (485). Voltage gating is another technique in which the supply access is cut to specific domains of the microprocessor chip by MOSFETs when the resources of these domains are not needed

In “A 2.60pj/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency” by Bo et al (2006), energy efficiency is explained through a two-stage micro architecture mitigating the effect of process variation in sub-threshold operation. Energy efficiency was tested through a designed sensor processor, referred to as the subliminal processor, which was optimized for energy-efficient sub-threshold operations.

The implementation of energy efficiency was achieved through re-characterizing the gates library at sub-threshold voltage: gates with more than 2 fan-ins were eliminated along with pass-transistors logic. In such a way, performance was increased, as opposed to the standard library, at a sub-threshold voltage (Zhai et al. 154). The minimization of the consumption of the SRAM was reached through a custom-designed, mux-based array structure. The adaptive control of sub-threshold voltage was tested using special level converted, leading to the conclusion that significant energy savings are obtained through applying adaptive frequency tuning.

In “Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation” by Ernst et al (2004), the implementation of low power consumption is argued to be effective through dynamic detection and correction of circuit timing errors. The approach, titled Razor, implies that the key supply of voltage will be monitored and adjusted according to error rate during operation (Ernst et al. 11). The benefit of such an approach against Dynamic Voltage Scaling (DVS) is that it cannot account for local voltage drops.

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The implementation of Razor is achieved at both the circuit level and architectural level. On the circuit level, the implementation of Razor implies a concept in which designing a pipeline stage where XOR gate compares the input of the main flip-flop and a logic stage going through a shadow latch, which augments each flip-flop in the design. Implementing combinational logic ensures that in case of an error, the instructions can be re-executed (12). Error recovery can be implemented through three approaches, cloak gating, counterflow pipelining, and micro rollback.


Thus, three articles presented the concept of low voltage digital logical designs. Low consumption can be reached through applying different techniques that reduced Vmin, varying the access to voltage supply, a combination of adaptive frequency tuning and custom processor designed for low energy, and combinational logic.

Works Cited

Ernst, Dan, et al. “Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation.” IEEE Micro 24.6 (2004): 10 – 20. Print.

Hanson, S., et al. “Ultralow-Voltage, Minimum-Energy CMOS.” IBM Journal of Research and Development 50.4/5 (2006): 469-90. Print.

Zhai, Bo, et al. “A 2.60pj/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency.” 2006 Symposium on VLSI Circuits (2006): 154 – 55. Print.

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