Introduction
In many engineering applications, there is a need for efficiency. Power management is an elemental strategy for improving efficiency. The idea is to reduce power consumption to the least possible value while ensuring performance is okay. In the design of digital logic, power scaling is a major way to achieve low voltage consumption.
Dynamic Voltage Scaling
One of the power scaling methods is “Dynamic Voltage Scaling” (DVS). In this technique, there is lowering of the clock of the processor to the minimum level required so that power supplied to the processor corresponds to the level of utilization of the processor i.e. low power supplied when idle and more power when active. This method saves energy, unlike a system that supplies constant power to the processor when active or idle. Critical voltage is a minimum level of voltage below which operation is impossible. The handicap of using this method is the difficulty in enabling a system to operate at multiple frequencies and multiple power levels simultaneously.
The factors affecting the performance of the system are global variables or local variables. Global variables affect the overall performance of the chip, while local variables affect certain parts of the chip. “Global variables include unexpected drops in voltage and fluctuations in temperature while local variables include cross-coupling noise, varying length of the gate of the FETs making the chip, and varying doping concentration,” (Hanson et al. 2). Shortcomings of this DVS technique call for a safety margin to guarantee stable performance. “Addition of a marginal voltage to critical voltage incorporates safety margin,” (Hanson et al. 2). However, the goal being to reduce power consumption means that the idea of safety margin contradicts the goal, there is an improvement over systems not applying DVS (Hanson et al. 1).
“Embedded inverter delay Chains” is one way to implement DVS. “The delay of the inverter chain predicts the critical path-delay of the circuit and tunes supply voltage to one of the processor chips,” (Hanson et al. 2). The voltage controller then “tunes the supply voltage to achieve the predetermined delay through the inverter chain,” when the processor is in operation,” (Hanson et al. 2). Hanson et al. note that this method has an advantage in that “voltage is adjusted dynamically to cater for global variations” (2). Demerits of the system are that it does not account for local variations and that the chain delay does not scale with voltage and temperature as anticipated from a theoretical analysis of the design. This method also calls for safety margin voltages, which reduce the amount of energy saved.
Razor method
The “razor method” is another DVS technique, which employs “dynamic detection and correction of speed path failures” (IEEE Micro 13). It tunes the supply voltage by comparing the output to input error. It operates as a simple feedback system. The error detection in return monitors the actual delay of the circuit. “This method provides for both local and global variations and does not experience disparities of voltage scaling,” (IEEE Micro 13). The overall result is that power saving is increased by about 40% as observed by 10 University of Michigan graduates who experimented using this method.
Subthreshold sensor
Compared to the DVS method analyzed above, this method saves more energy. In particular, the “subliminal processor” which is an implementation of such a sensor operates on the fact that a CMOS attains maximum energy efficiency when leakage energy and active energy have equal and opposite sensitivity to the voltage. This is attained at a minimum voltage Vmin that is less than the threshold voltage of a MOS device. The voltage can scale up to this Vmin value. Scaling any further below this reduces the amount of energy saved because leakage voltage dominates voltage consumption. Tuning voltage adaptively is less efficient as proved experimentally and adaptive frequency tuning is used instead.
“Ultra-low voltage minimum energy CMOS” is also another way of implementing the sub-threshold sensor. It operates like the subliminal processor only that at Vmin, Random Dopant Fluctuation is rampant (Hanson et al 474).
Reduced voltage consumption can also be achieved by maximizing transistor usage using “Adaptive Body Biasing” and “Voltage gating” methods.. “Long paths or paths with low activity increase effective idle time and increase Vmin.” (Hanson et al 475). An increased Vmin means increased leakage hence power loss. These two methods reduce leakage by “lowering Vmin in the idle periods.”
Adaptive Body Biasing (ABB)
ABB “modulates the voltage of the substrate to dynamically change the static-power-vs. Active performance tradeoff asserted by threshold voltage”. (Hanson et al 481). “Machine state requirements are anticipated via instruction-look- head techniques, and substrate voltages are adjusted to optimize power without dramatically affecting performance.” (Hanson et al 483)
Voltage gating
In this method, “large onboard header and footer MOSFETs provide power to specific domains of the microprocessor chip. When the resource in these domains is no longer needed, their supply access is cut by these devices.” (Hanson et al 486).
Conclusion
From the above discussion, substantial energy saving in digital logic systems can be realized with the subthreshold method offering the best performance.
Works cited
“Razor: circuit-level correction of timing errors for low-power operation.”IEEE Micro (2004): 10-20. JSTOR.
Hanson, Scott, Zhai Bo, Bernstein Kerry, Blaauw David, Bryant Andres, Chang Leland, Das Koushik, Haensch Wilfred, Nowak Edward, and Sylvester Dennis. “Ultralow-voltage, minimum-energy CMOS” International Business Machine Corporation 50.4/5 (2006): 469-88.
Zhai, Bo, Leyla Nazhandali, Javin Olson, Ana Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, David Blaauw, and Todd Austin. “A 2.60pJ/Inst Sub Threshold Sensor Processor for Optimal Energy Efficiency”. The University of Michigan. 1-2JSTOR.